Tesla Cuts RAM on AI5 and AI6 Chips to Boost Production
Elon Musk stated the memory reduction is necessary to secure enough volume for Optimus robot manufacturing.
Tesla is reducing the memory capacity on its upcoming AI5 and AI6 chips to facilitate higher production volumes, particularly for the Optimus humanoid robot. According to Elon Musk, these adjustments are critical to overcoming supply constraints and reducing per-unit costs.
What Happened
Musk announced on X that Tesla initially planned to cut RAM in half for the AI5 chip and by a third for the AI6 chip. However, the AI5 specification was later adjusted to 96GB of LPDDR5, a slight increase from the initially proposed 72GB, to avoid using the lowest memory variant of the LPDDR5 standard. Consequently, AI5 will have one-third less memory than originally planned, matching the reduction applied to AI6, which will feature 144GB of LPDDR6. Musk stated that these changes are "the only way to get enough volume for Optimus production" and noted that the move significantly reduces costs.
Why It Matters
Despite the reduced memory capacity, Musk asserts that the impact on Optimus performance will be negligible because memory bandwidth, rather than total capacity, is the primary bottleneck for these systems, and overall bandwidth remains unchanged. This strategy contrasts with industry estimates, such as those from Micron, which suggest humanoid robots could require around 200GB of RAM. By prioritizing bandwidth and cost efficiency over raw capacity, Tesla aims to scale production amidst tight global memory supplies. Additionally, AI5 is not slated for immediate deployment in passenger vehicles; Musk confirmed that Optimus and AI training clusters will receive priority, with the hardware potentially trickling down to cars later. Current vehicle autonomy relies on AI4 hardware, which Musk maintains is sufficient for unsupervised driving.
The Bottom Line
Tesla’s decision to trim RAM on AI5 and AI6 chips reflects a strategic trade-off to accelerate Optimus production and lower costs, relying on bandwidth efficiency rather than increased memory capacity to maintain performance standards.
